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NXP Semiconductors /LPC18xx /EMC /STATUS

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Interpret as STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IDLE)B0 (EMPTY)S0 (NORMAL_MODE)SA 0RESERVED

B=IDLE, S=EMPTY, SA=NORMAL_MODE

Description

Provides EMC status information.

Fields

B

Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:

0 (IDLE): Idle. EMC is idle (warm reset value).

1 (BUSY): Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value).
S

Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:

0 (EMPTY): Empty. Write buffers empty (POR reset value)

1 (DATA): Data. Write buffers contain data.
SA

Self-refresh acknowledge. This bit indicates the operating mode of the EMC:

0 (NORMAL_MODE): Normal mode.

1 (SELF_REFRESH_MODE): Self-refresh mode. (POR reset value.)
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data